Analog Mixed-Signal Design and Verification Engineer

Elsys Eastern Europe d.o.o.

Novi Sad, Beograd, Rad od kuće
Rok za prijavu: 23.01.2022.
Postavljeno: 26.10.2021.
Prakse
Nije potrebno radno iskustvo
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The final list of selected candidates will be announced by 7th February.

Internship is planned to start mid-March after the exams, however, due to the situation exact date will be announced in a timely manner.

Analog Mixed-Signal Design and Verification Engineer

You will be a part of an analog design and modeling team, constituted of engineers with a different level of experience, from experts to juniors. Involvement in analog IP models development, model calibration (model vs schematic) and close interaction with other IC implementation teams in order to achieve IC implementation milestones. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows. Selected candidates will receive full training and support from our experienced engineers. The project can be a subject of a bachelor/master thesis or seminar paper.

  • Selected candidates will be engaged in:
    • Development of Verilog A/AMS models of AMS IP
    • Analog and mixed-signal circuits analysis
    • Development of AMS design verification environment
    • Using Cadence toolchain for AMS verification
  • Intern will receive full training and support from our experienced engineers.
  • Duration of internship is 4 months and will begin after exams or differently defined with candidate
  • Full time internship 40h a week or differently defined with candidate
  • Internship project can be subject of a bachelor/master thesis or seminar paper
  • Interns will receive monthly compensation
  • Company will provide accommodation if interns are outside of Belgrade or Novi Sad

Internship Timeline

1 week (lectures + project)

  • Digital design

3-4 weeks (lectures + Lab practice)

  • System Verilog and UVM

1 week

  • UVC creation of a given module

≈10 weeks (2 lectures + Lab practice + Final model)

  • Analog modeling Verilog – AMS

2 weeks

  • Model integration into UVM environment

Employee Benefits:

  • Full Remote
  • Professional, Young % Dynamic Team
  • Prifessional Development Opportunities
  • Competitve Salaries % Benefits
  • Additional Helth Insurance, Sport & Social Activities
  • International Work Environment & Traveling Opportunities
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