Digital Design Verification Engineer

Elsys Eastern Europe d.o.o.

Novi Sad, Beograd, Rad od kuće
Rok za prijavu: 23.01.2022.
Postavljeno: 26.10.2021.
Prakse
Nije potrebno radno iskustvo
elsys logo fb
Klikom na dugme Konkuriši, dalji tok konkurisanja nastavljaš na eksternom sajtu.

The final list of selected candidates will be announced by 7th February.

Internship is planned to start mid-March after the exams, however, due to the situation exact date will be announced in a timely manner.

Digital Design Verification Engineer

You will be a part of a digital/mixed-signal design verification team, constituted of verification engineers with different level of experience, from verification experts to verification juniors. In order to achieve IC implementation milestones you will be involved in verification methodology establishment, verification plan creation, development of verification environment and close interaction with other IC implementation teams. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.

  • Selected candidates will be engaged in development of a digital/mixed-signal verification environment including:
    • architecture definition
    • verification environment implementation in SystemVerilog
    • verification planning
    • full verification in accordance with UVM methodology (SystemVerilog)
  • Intern will receive full training and support from our experienced engineers.
  • Duration of internship is 3 months and will begin after exams or differently defined with candidate
  • Full time internship 40h a week or differently defined with candidate
  • Internship project can be subject of a bachelor/master thesis or seminar paper
  • Interns will receive monthly compensation
  • Company will provide accommodation if interns are outside of Belgrade or Novi Sad

Internship Timeline

1 week (Lectures + Lab practice)

  • Digital design

3 weeks (Lectures + Lab practice)

  • System Verilog and UVM

Project oriented traininguntil the end of the program

Project oriented traininguntil the end of the program

Employee Benefits:

  • Full Remote
  • Professional, Young % Dynamic Team
  • Prifessional Development Opportunities
  • Competitve Salaries % Benefits
  • Additional Helth Insurance, Sport & Social Activities
  • International Work Environment & Traveling Opportunities

Required Skills and Qualifications:

  • Final Year Student Or Fresh Graduate With B.Sc. Or M.Sc. Degree In Electrical Engineering
  • Motivated, Proactive, Hard Working
  • Relevant Courses/Knowledge: Basics Of Digital Electronics, Programming,
  • FPGA Basics, Microcontroller Architecture
  • Good Knowledge Of English Language
Profil poslodavca
Konkuriši

Slični poslovi

Technical Support Engineer

Huawei Technologies d.o.o.

Beograd
04.06.2022.

Site Reliability Engineer

Ipro Solutions d.o.o.

Rad od kuće
07.06.2022.

Nastavkom korišćenja sajta smatramo da prihvataš korišćenje kolačića. Saznaj više